In order to meet the requirements of portable electronic devices for minimization and high speed operation with more functions, the development of new technologies has been changed in quarterly bases. Therefore, multi-chip packages have been quite popular to increase the functions or/and the memory capacities within a single package. Chip-on-chip stacked packages have been developed to package two or more chips vertically stacked on each another within a single package to expect a smaller footprint.
As shown in FIG. 1, a conventional multi-chip package (MCP) 100 with chip-on-chip configuration is to vertically stack a plurality of chips 120 and 150 on a substrate 110. Generally speaking, during the packaging processes of the MCP, a first chip 120 is disposed on the substrate 110 by an adhesive 130, then the bonding pads 123 on the first active surface 121 of the first chip 120 are electrically connected to the bonding fingers 113 on the substrate 110 by a plurality of first bonding wires 141 formed by wire bonding. Then, a second chip 150 is disposed on top of the first chip 120 where a FOW adhesive (Film On Wire) adhesive 162 is pre-disposed on the first active surface 121 of the first chip 120 by dispensing or by printing. The FOW adhesive 162 is attached to the back surface 152 of the second chip 150 and partially encapsulates the first bonding wires 141 where FOW adhesive 162 has a thickness more than the loop heights of the first bonding wires 141. However, the chip bonding operation of the second chip 150 decreases the thickness of the FOW adhesive 162 so that the first bonding wires 141 may physically contact the back surface 152 of the second chip 150. After curing the FOW adhesive 162, the FOW adhesive 162 can support the second chip 150 for further wire bonding processes. After stacking the second chip 150, the second bonding pads 153 of the second chip 150 are electrically connected to the bonding fingers 113 by a plurality of second bonding wires 142 formed by wire bonding. A molding compound 180 is formed on the substrate 110 to encapsulate the first chip 120, the second chip 150, the bonding wires 141 and 142.
Since the FOW adhesive is very expensive, there are several attempts to reduce the cost of FOW adhesive where reducing the thickness of FOW adhesive is one of them. However, when the thickness of FOW adhesive 162 is reduced, the first bonding wires 141 would more easily contact the back surface 152 of the second chip 150 leading to electrical short, especially in packages with long bonding wires. Furthermore, during disposing the second chip 150 to the first chip 120, the FOW adhesive 162 is like paste where bubbles easily trap inside the FOW adhesive 162 due to the present of bonding wires 141. Once many bubbles are trapped inside the FOW adhesive 162, the encapsulation and adhesion of the FOW adhesive 162 are greatly reduced leading to poor adhesion between the first chip 120 and the second chip 150. Moreover, after curing the FOW adhesive 162, the trapped bubbles experience raised temperature during IC operation and rapidly expand causing popcorn leading to delamination and cracking between the chips so that the MCP would be damaged and failed mechanically and electrically.